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wdt.h
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1 /* Copyright (c) 2002, 2004 Marek Michalkiewicz
2  Copyright (c) 2005, 2006, 2007 Eric B. Weddington
3  All rights reserved.
4 
5  Redistribution and use in source and binary forms, with or without
6  modification, are permitted provided that the following conditions are met:
7 
8  * Redistributions of source code must retain the above copyright
9  notice, this list of conditions and the following disclaimer.
10 
11  * Redistributions in binary form must reproduce the above copyright
12  notice, this list of conditions and the following disclaimer in
13  the documentation and/or other materials provided with the
14  distribution.
15 
16  * Neither the name of the copyright holders nor the names of
17  contributors may be used to endorse or promote products derived
18  from this software without specific prior written permission.
19 
20  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  POSSIBILITY OF SUCH DAMAGE. */
31 
32 /* $Id$ */
33 
34 /*
35  avr/wdt.h - macros for AVR watchdog timer
36  */
37 
38 #ifndef _AVR_WDT_H_
39 #define _AVR_WDT_H_
40 
41 #include <avr/io.h>
42 #include <stdint.h>
43 
44 /** \file */
45 /** \defgroup avr_watchdog <avr/wdt.h>: Watchdog timer handling
46  \code #include <avr/wdt.h> \endcode
47 
48  This header file declares the interface to some inline macros
49  handling the watchdog timer present in many AVR devices. In order
50  to prevent the watchdog timer configuration from being
51  accidentally altered by a crashing application, a special timed
52  sequence is required in order to change it. The macros within
53  this header file handle the required sequence automatically
54  before changing any value. Interrupts will be disabled during
55  the manipulation.
56 
57  \note Depending on the fuse configuration of the particular
58  device, further restrictions might apply, in particular it might
59  be disallowed to turn off the watchdog timer.
60 
61  Note that for newer devices (ATmega88 and newer, effectively any
62  AVR that has the option to also generate interrupts), the watchdog
63  timer remains active even after a system reset (except a power-on
64  condition), using the fastest prescaler value (approximately 15
65  ms). It is therefore required to turn off the watchdog early
66  during program startup, the datasheet recommends a sequence like
67  the following:
68 
69  \code
70  #include <stdint.h>
71  #include <avr/wdt.h>
72 
73  uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
74 
75  void get_mcusr(void) \
76  __attribute__((naked)) \
77  __attribute__((section(".init3")));
78  void get_mcusr(void)
79  {
80  mcusr_mirror = MCUSR;
81  MCUSR = 0;
82  wdt_disable();
83  }
84  \endcode
85 
86  Saving the value of MCUSR in \c mcusr_mirror is only needed if the
87  application later wants to examine the reset source, but in particular,
88  clearing the watchdog reset flag before disabling the
89  watchdog is required, according to the datasheet.
90 */
91 
92 /**
93  \ingroup avr_watchdog
94  Reset the watchdog timer. When the watchdog timer is enabled,
95  a call to this instruction is required before the timer expires,
96  otherwise a watchdog-initiated device reset will occur.
97 */
98 
99 #define wdt_reset() __asm__ __volatile__ ("wdr")
100 
101 
102 #if defined(WDP3)
103 # define _WD_PS3_MASK _BV(WDP3)
104 #else
105 # define _WD_PS3_MASK 0x00
106 #endif
107 
108 #if defined(WDTCSR)
109 # define _WD_CONTROL_REG WDTCSR
110 #elif defined(WDTCR)
111 # define _WD_CONTROL_REG WDTCR
112 #else
113 # define _WD_CONTROL_REG WDT
114 #endif
115 
116 #if defined(WDTOE)
117 #define _WD_CHANGE_BIT WDTOE
118 #else
119 #define _WD_CHANGE_BIT WDCE
120 #endif
121 
122 
123 /**
124  \ingroup avr_watchdog
125  Enable the watchdog timer, configuring it for expiry after
126  \c timeout (which is a combination of the \c WDP0 through
127  \c WDP2 bits to write into the \c WDTCR register; For those devices
128  that have a \c WDTCSR register, it uses the combination of the \c WDP0
129  through \c WDP3 bits).
130 
131  See also the symbolic constants \c WDTO_15MS et al.
132 */
133 
134 
135 #if defined(__AVR_XMEGA__)
136 
137 /*
138  wdt_enable(timeout) for xmega devices
139 ** write signature (CCP_IOREG_gc) that enables change of protected I/O
140  registers to the CCP register
141 ** At the same time,
142  1) set WDT change enable (WDT_CEN_bm)
143  2) enable WDT (WDT_ENABLE_bm)
144  3) set timeout (timeout)
145 ** Synchronization starts when ENABLE bit of WDT is set. So, wait till it
146  finishes (SYNCBUSY of STATUS register is automatically cleared after the
147  sync is finished).
148 */
149 #define wdt_enable(timeout) \
150 do { \
151 uint8_t temp; \
152 __asm__ __volatile__ ( \
153  "in __tmp_reg__, %[rampd]" "\n\t" \
154  "out %[rampd], __zero_reg__" "\n\t" \
155  "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \
156  "sts %[wdt_reg], %[wdt_enable_timeout]" "\n\t" \
157  "1:lds %[tmp], %[wdt_status_reg]" "\n\t" \
158  "sbrc %[tmp], %[wdt_syncbusy_bit]" "\n\t" \
159  "rjmp 1b" "\n\t" \
160  "out %[rampd], __tmp_reg__" "\n\t" \
161  : [tmp] "=r" (temp) \
162  : [rampd] "I" (_SFR_IO_ADDR(RAMPD)), \
163  [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \
164  [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \
165  [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRL)), \
166  [wdt_enable_timeout] "r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | timeout)), \
167  [wdt_status_reg] "n" (_SFR_MEM_ADDR(WDT_STATUS)), \
168  [wdt_syncbusy_bit] "I" (WDT_SYNCBUSY_bm) \
169  : "r0" \
170 ); \
171 } while(0)
172 
173 #define wdt_disable() \
174 __asm__ __volatile__ ( \
175  "in __tmp_reg__, %[rampd]" "\n\t" \
176  "out %[rampd], __zero_reg__" "\n\t" \
177  "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \
178  "sts %[wdt_reg], %[disable_mask]" "\n\t" \
179  "out %[rampd], __tmp_reg__" "\n\t" \
180  : \
181  : [rampd] "I" (_SFR_IO_ADDR(RAMPD)), \
182  [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \
183  [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \
184  [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRL)), \
185  [disable_mask] "r" ((uint8_t)((~WDT_ENABLE_bm) | WDT_CEN_bm)) \
186  : "r0" \
187 );
188 
189 #elif defined(__AVR_TINY__)
190 
191 #define wdt_enable(value) \
192 __asm__ __volatile__ ( \
193  "in __tmp_reg__,__SREG__" "\n\t" \
194  "cli" "\n\t" \
195  "wdr" "\n\t" \
196  "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
197  "out %[WDTREG],%[WDVALUE]" "\n\t" \
198  "out __SREG__,__tmp_reg__" "\n\t" \
199  : /* no outputs */ \
200  : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \
201  [SIGNATURE] "r" ((uint8_t)0xD8), \
202  [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
203  [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) \
204  | _BV(WDE) | (value & 0x07) )) \
205  : "r16" \
206 )
207 
208 #define wdt_disable() \
209 do { \
210 uint8_t temp_wd; \
211 __asm__ __volatile__ ( \
212  "in __tmp_reg__,__SREG__" "\n\t" \
213  "cli" "\n\t" \
214  "wdr" "\n\t" \
215  "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
216  "in %[TEMP_WD],%[WDTREG]" "\n\t" \
217  "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" \
218  "out %[WDTREG],%[TEMP_WD]" "\n\t" \
219  "out __SREG__,__tmp_reg__" "\n\t" \
220  : /*no output */ \
221  : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \
222  [SIGNATURE] "r" ((uint8_t)0xD8), \
223  [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
224  [TEMP_WD] "d" (temp_wd), \
225  [WDVALUE] "n" (1 << WDE) \
226  : "r16" \
227 ); \
228 }while(0)
229 
230 #elif defined(CCP)
231 
232 static __inline__
233 __attribute__ ((__always_inline__))
234 void wdt_enable (const uint8_t value)
235 {
236  if (!_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P (_WD_CONTROL_REG))
237  {
238  __asm__ __volatile__ (
239  "in __tmp_reg__,__SREG__" "\n\t"
240  "cli" "\n\t"
241  "wdr" "\n\t"
242  "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t"
243  "sts %[WDTREG],%[WDVALUE]" "\n\t"
244  "out __SREG__,__tmp_reg__" "\n\t"
245  : /* no outputs */
246  : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)),
247  [SIGNATURE] "r" ((uint8_t)0xD8),
248  [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
249  [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
250  | _BV(WDE) | (value & 0x07) ))
251  : "r0"
252  );
253  }
254  else if (!_SFR_IO_REG_P (CCP) && _SFR_IO_REG_P (_WD_CONTROL_REG))
255  {
256  __asm__ __volatile__ (
257  "in __tmp_reg__,__SREG__" "\n\t"
258  "cli" "\n\t"
259  "wdr" "\n\t"
260  "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t"
261  "out %[WDTREG],%[WDVALUE]" "\n\t"
262  "out __SREG__,__tmp_reg__" "\n\t"
263  : /* no outputs */
264  : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)),
265  [SIGNATURE] "r" ((uint8_t)0xD8),
266  [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
267  [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
268  | _BV(WDE) | (value & 0x07) ))
269  : "r0"
270  );
271  }
272  else if (_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P (_WD_CONTROL_REG))
273  {
274  __asm__ __volatile__ (
275  "in __tmp_reg__,__SREG__" "\n\t"
276  "cli" "\n\t"
277  "wdr" "\n\t"
278  "out %[CCPADDRESS],%[SIGNATURE]" "\n\t"
279  "sts %[WDTREG],%[WDVALUE]" "\n\t"
280  "out __SREG__,__tmp_reg__" "\n\t"
281  : /* no outputs */
282  : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)),
283  [SIGNATURE] "r" ((uint8_t)0xD8),
284  [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
285  [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
286  | _BV(WDE) | (value & 0x07) ))
287  : "r0"
288  );
289  }
290  else
291  {
292  __asm__ __volatile__ (
293  "in __tmp_reg__,__SREG__" "\n\t"
294  "cli" "\n\t"
295  "wdr" "\n\t"
296  "out %[CCPADDRESS],%[SIGNATURE]" "\n\t"
297  "out %[WDTREG],%[WDVALUE]" "\n\t"
298  "out __SREG__,__tmp_reg__" "\n\t"
299  : /* no outputs */
300  : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)),
301  [SIGNATURE] "r" ((uint8_t)0xD8),
302  [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
303  [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
304  | _BV(WDE) | (value & 0x07) ))
305  : "r0"
306  );
307  }
308 }
309 
310 static __inline__
311 __attribute__ ((__always_inline__))
312 void wdt_disable (void)
313 {
314  if (!_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P(_WD_CONTROL_REG))
315  {
316  uint8_t temp_wd;
317  __asm__ __volatile__ (
318  "in __tmp_reg__,__SREG__" "\n\t"
319  "cli" "\n\t"
320  "wdr" "\n\t"
321  "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t"
322  "lds %[TEMP_WD],%[WDTREG]" "\n\t"
323  "cbr %[TEMP_WD],%[WDVALUE]" "\n\t"
324  "sts %[WDTREG],%[TEMP_WD]" "\n\t"
325  "out __SREG__,__tmp_reg__" "\n\t"
326  : /*no output */
327  : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)),
328  [SIGNATURE] "r" ((uint8_t)0xD8),
329  [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
330  [TEMP_WD] "d" (temp_wd),
331  [WDVALUE] "n" (1 << WDE)
332  : "r0"
333  );
334  }
335  else if (!_SFR_IO_REG_P (CCP) && _SFR_IO_REG_P(_WD_CONTROL_REG))
336  {
337  uint8_t temp_wd;
338  __asm__ __volatile__ (
339  "in __tmp_reg__,__SREG__" "\n\t"
340  "cli" "\n\t"
341  "wdr" "\n\t"
342  "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t"
343  "in %[TEMP_WD],%[WDTREG]" "\n\t"
344  "cbr %[TEMP_WD],%[WDVALUE]" "\n\t"
345  "out %[WDTREG],%[TEMP_WD]" "\n\t"
346  "out __SREG__,__tmp_reg__" "\n\t"
347  : /*no output */
348  : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)),
349  [SIGNATURE] "r" ((uint8_t)0xD8),
350  [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
351  [TEMP_WD] "d" (temp_wd),
352  [WDVALUE] "n" (1 << WDE)
353  : "r0"
354  );
355  }
356  else if (_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P(_WD_CONTROL_REG))
357  {
358  uint8_t temp_wd;
359  __asm__ __volatile__ (
360  "in __tmp_reg__,__SREG__" "\n\t"
361  "cli" "\n\t"
362  "wdr" "\n\t"
363  "out %[CCPADDRESS],%[SIGNATURE]" "\n\t"
364  "lds %[TEMP_WD],%[WDTREG]" "\n\t"
365  "cbr %[TEMP_WD],%[WDVALUE]" "\n\t"
366  "sts %[WDTREG],%[TEMP_WD]" "\n\t"
367  "out __SREG__,__tmp_reg__" "\n\t"
368  : /*no output */
369  : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)),
370  [SIGNATURE] "r" ((uint8_t)0xD8),
371  [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
372  [TEMP_WD] "d" (temp_wd),
373  [WDVALUE] "n" (1 << WDE)
374  : "r0"
375  );
376  }
377  else
378  {
379  uint8_t temp_wd;
380  __asm__ __volatile__ (
381  "in __tmp_reg__,__SREG__" "\n\t"
382  "cli" "\n\t"
383  "wdr" "\n\t"
384  "out %[CCPADDRESS],%[SIGNATURE]" "\n\t"
385  "in %[TEMP_WD],%[WDTREG]" "\n\t"
386  "cbr %[TEMP_WD],%[WDVALUE]" "\n\t"
387  "out %[WDTREG],%[TEMP_WD]" "\n\t"
388  "out __SREG__,__tmp_reg__" "\n\t"
389  : /*no output */
390  : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)),
391  [SIGNATURE] "r" ((uint8_t)0xD8),
392  [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
393  [TEMP_WD] "d" (temp_wd),
394  [WDVALUE] "n" (1 << WDE)
395  : "r0"
396  );
397  }
398 }
399 
400 #else
401 
402 static __inline__
403 __attribute__ ((__always_inline__))
404 void wdt_enable (const uint8_t value)
405 {
406  if (_SFR_IO_REG_P (_WD_CONTROL_REG))
407  {
408  __asm__ __volatile__ (
409  "in __tmp_reg__,__SREG__" "\n\t"
410  "cli" "\n\t"
411  "wdr" "\n\t"
412  "out %0, %1" "\n\t"
413  "out __SREG__,__tmp_reg__" "\n\t"
414  "out %0, %2" "\n \t"
415  : /* no outputs */
416  : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
417  "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
418  "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
419  _BV(WDE) | (value & 0x07)) )
420  : "r0"
421  );
422  }
423  else
424  {
425  __asm__ __volatile__ (
426  "in __tmp_reg__,__SREG__" "\n\t"
427  "cli" "\n\t"
428  "wdr" "\n\t"
429  "sts %0, %1" "\n\t"
430  "out __SREG__,__tmp_reg__" "\n\t"
431  "sts %0, %2" "\n \t"
432  : /* no outputs */
433  : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
434  "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
435  "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
436  _BV(WDE) | (value & 0x07)) )
437  : "r0"
438  );
439  }
440 }
441 
442 static __inline__
443 __attribute__ ((__always_inline__))
444 void wdt_disable (void)
445 {
446  if (_SFR_IO_REG_P (_WD_CONTROL_REG))
447  {
448  uint8_t register temp_reg;
449  __asm__ __volatile__ (
450  "in __tmp_reg__,__SREG__" "\n\t"
451  "cli" "\n\t"
452  "wdr" "\n\t"
453  "in %[TEMPREG],%[WDTREG]" "\n\t"
454  "ori %[TEMPREG],%[WDCE_WDE]" "\n\t"
455  "out %[WDTREG],%[TEMPREG]" "\n\t"
456  "out %[WDTREG],__zero_reg__" "\n\t"
457  "out __SREG__,__tmp_reg__" "\n\t"
458  : [TEMPREG] "=d" (temp_reg)
459  : [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
460  [WDCE_WDE] "n" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE)))
461  : "r0"
462  );
463  }
464  else
465  {
466  uint8_t register temp_reg;
467  __asm__ __volatile__ (
468  "in __tmp_reg__,__SREG__" "\n\t"
469  "cli" "\n\t"
470  "wdr" "\n\t"
471  "lds %[TEMPREG],%[WDTREG]" "\n\t"
472  "ori %[TEMPREG],%[WDCE_WDE]" "\n\t"
473  "sts %[WDTREG],%[TEMPREG]" "\n\t"
474  "sts %[WDTREG],__zero_reg__" "\n\t"
475  "out __SREG__,__tmp_reg__" "\n\t"
476  : [TEMPREG] "=d" (temp_reg)
477  : [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
478  [WDCE_WDE] "n" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE)))
479  : "r0"
480  );
481  }
482 }
483 
484 #endif
485 
486 
487 /**
488  \ingroup avr_watchdog
489  Symbolic constants for the watchdog timeout. Since the watchdog
490  timer is based on a free-running RC oscillator, the times are
491  approximate only and apply to a supply voltage of 5 V. At lower
492  supply voltages, the times will increase. For older devices, the
493  times will be as large as three times when operating at Vcc = 3 V,
494  while the newer devices (e. g. ATmega128, ATmega8) only experience
495  a negligible change.
496 
497  Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms,
498  500 ms, 1 s, 2 s. (Some devices also allow for 4 s and 8 s.)
499  Symbolic constants are formed by the prefix
500  \c WDTO_, followed by the time.
501 
502  Example that would select a watchdog timer expiry of approximately
503  500 ms:
504  \code
505  wdt_enable(WDTO_500MS);
506  \endcode
507 */
508 #define WDTO_15MS 0
509 
510 /** \ingroup avr_watchdog
511  See \c WDTO_15MS */
512 #define WDTO_30MS 1
513 
514 /** \ingroup avr_watchdog
515  See \c WDTO_15MS */
516 #define WDTO_60MS 2
517 
518 /** \ingroup avr_watchdog
519  See \c WDTO_15MS */
520 #define WDTO_120MS 3
521 
522 /** \ingroup avr_watchdog
523  See \c WDTO_15MS */
524 #define WDTO_250MS 4
525 
526 /** \ingroup avr_watchdog
527  See \c WDTO_15MS */
528 #define WDTO_500MS 5
529 
530 /** \ingroup avr_watchdog
531  See \c WDTO_15MS */
532 #define WDTO_1S 6
533 
534 /** \ingroup avr_watchdog
535  See \c WDTO_15MS */
536 #define WDTO_2S 7
537 
538 #if defined(__DOXYGEN__) || defined(WDP3)
539 
540 /** \ingroup avr_watchdog
541  See \c WDTO_15MS
542  Note: This is only available on the
543  ATtiny2313,
544  ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
545  ATtiny25, ATtiny45, ATtiny85,
546  ATtiny261, ATtiny461, ATtiny861,
547  ATmega48, ATmega88, ATmega168,
548  ATmega48P, ATmega88P, ATmega168P, ATmega328P,
549  ATmega164P, ATmega324P, ATmega644P, ATmega644,
550  ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
551  ATmega8HVA, ATmega16HVA, ATmega32HVB,
552  ATmega406, ATmega1284P,
553  ATmega256RFR2, ATmega128RFR2, ATmega64RFR2,
554  ATmega2564RFR2, ATmega1284RFR2, ATmega644RFR2,
555  AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
556  AT90PWM81, AT90PWM161,
557  AT90USB82, AT90USB162,
558  AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
559  ATtiny48, ATtiny88.
560  */
561 #define WDTO_4S 8
562 
563 /** \ingroup avr_watchdog
564  See \c WDTO_15MS
565  Note: This is only available on the
566  ATtiny2313,
567  ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
568  ATtiny25, ATtiny45, ATtiny85,
569  ATtiny261, ATtiny461, ATtiny861,
570  ATmega48, ATmega48A, ATmega48PA, ATmega88, ATmega168,
571  ATmega48P, ATmega88P, ATmega168P, ATmega328P,
572  ATmega164P, ATmega324P, ATmega644P, ATmega644,
573  ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
574  ATmega8HVA, ATmega16HVA, ATmega32HVB,
575  ATmega406, ATmega1284P,
576  ATmega256RFR2, ATmega128RFR2, ATmega64RFR2,
577  ATmega2564RFR2, ATmega1284RFR2, ATmega644RFR2,
578  AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
579  AT90PWM81, AT90PWM161,
580  AT90USB82, AT90USB162,
581  AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
582  ATtiny48, ATtiny88,
583  ATxmega16a4u, ATxmega32a4u,
584  ATxmega16c4, ATxmega32c4,
585  ATxmega128c3, ATxmega192c3, ATxmega256c3.
586  */
587 #define WDTO_8S 9
588 
589 #endif /* defined(__DOXYGEN__) || defined(WDP3) */
590 
591 
592 #endif /* _AVR_WDT_H_ */
unsigned char uint8_t
Definition: stdint.h:79
#define _BV(bit)
Definition: sfr_defs.h:208
static __inline__ __attribute__((__always_inline__)) void wdt_enable(const uint8_t value)
Definition: wdt.h:403

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